The present disclosure relates to circuit design and, more particularly, to a method for manufacturing an integrated circuit with the aid of a pattern based timing database indicating aging effects.
Device aging refers to device performance degradation over time. For example, when a constant electric field is applied to a gate of a transistor, a phenomenon called negative bias temperature instability (NBTI) can cause a buildup of charge in a gate dielectric, which in turn degrades a threshold voltage of the transistor. As a result, transistor aging caused by NBTI can lead to low switching speeds and cell delay degradation over time. Other degenerative mechanisms, such as hot carrier injection (HCl) and time-dependent dioxide breakdown (TDDB), can also cause transistor aging.
As an operating voltage is not scaled at the same rate as the scaling down of a device size, an electric filed applied to a device will increase, resulting in worse aging behavior. Integrated circuit performance degradation due to aging effects is therefore eating up scaling benefits in fin field-effect transistor (FinFET) technology.